The following table summarizes the superscalar execution capabilities of 32-bit PA-RISC processors.
nokeep tab (:) ; l l l _ _ _ l l l . CPU:Units:Bundles 7100:1 integer ALU:load-store/fp :1 FP :int/fp : :branch/* 7100LC:2 integer ALU:load-store/int :1 FP :load-store/fp : :int/fp : :branch/* 7200:2 integer ALU:load-store/int :1 FP :load-store/fp : :int/int : :int/fp : :branch/* 7300LC:2 integer ALU:load-store/int :1 FP :load-store/fp : :int/fp : :branch/*
In conclusion, all of the above CPUs are dual-issue, or 2-way superscalar, with the exception that on CPUs with two integer ALUs only one of these units is capable of doing shift, load/store, and test operations. Additionally, there are several kinds of restrictions placed upon the superscalar execution:
For the purpose of showing which instructions are allowed to proceed together through the pipeline, they are divided into classes:
tab (:) ; l l _ _ l l . Class:Description flop:floating point operation ldst:loads and stores flex:integer ALU mm:shifts, extracts and deposits nul:might nullify successor bv:BV, BE br:other branches fsys:FTEST and FP status/exception sys:system control instructions
For CPUs with two integer ALUs (7100LC, 7200, 7300LC), the following table lists the instructions which are allowed to be executed concurrently:
tab (:) ; l l _ _ l l . First:Second instruction flop: + ldst/flex/mm/nul/bv/br ldst: + flop/flex/mm/nul/br flex: + flop/ldst/flex/mm/nul/br/fsys mm: + flop/ldst/flex/fsys nul: + flop sys: never bundled
ldst + ldst is also possible under certain circumstances, which is then called "double word load/store".
The following restrictions are placed upon the superscalar execution:
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An instruction that modifies a register will not be bundled with another instruction that takes this register as operand. Exception: a flop can be bundled with an FP store of the flop's result register.
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An FP load to one word of a doubleword register will not be bundled with a flop that uses the other doubleword of this register.
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A flop will not be bundled with an FP load if both instructions have the same target register.
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An instruction that could set the carry/borrow bits will not be bundled with an instruction that uses carry/borrow bits.
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An instruction which is in the delay slot of a branch is never bundled with other instructions.
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An instruction which is at an odd word address and executed as a target of a taken branch is never bundled.
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An instruction which might nullify its successor is never bundled with this successor. Only if the successor is a flop instruction is this bundle allowed.