The
nmi interface lets the kernel establish handlers for x86 Non-Maskable Interrupts (NMIs). An NMI signals to the processor an exception on a processor, memory controller, or I/O bus that is irrecoverable or else needs attention at a high priority. A “debug switch” or a performance/watchdog timer may also trigger an NMI.
An NMI handler will run to completion on the same processor where it began without being preempted by any thread or interrupt except for another NMI. An NMI handler must prepare for re-entry. An NMI handler may run simultaneously on more than one CPU.
Synchronizing access to a shared data structure from an NMI handler is a different challenge than synchronizing access from hardware/software interrupt routines or from kernel threads. An NMI handler may not perform any operation that may sleep, acquire a mutex, or schedule a software interrupt. An NMI handler may use
atomic_ops(3). An NMI handler may reference per-CPU storage (
percpu(9)).
An NMI handler may not write to the kernel message buffer.